1. Field of the Invention
The present invention relates to packaging substrates and fabrication methods thereof, and more particularly, to a packaging substrate which facilitates thinning of package structures and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. To minimize semiconductor packages, packaging substrates carrying semiconductor chips are required to have reduced thicknesses. Such a packaging substrate can be made of a hard material or a soft material. Packaging substrates used in ball grid array (BGA) packages are generally made of a hard material.
FIGS. 1A to 1C are schematic cross-sectional views showing a fabrication method of a packaging substrate 1 having double-layer circuits.
Referring to FIG. 1A, a core layer 10 is provided. The core layer 10 has a first surface 10a having a first metal layer 11a disposed thereon, a second surface 10b opposite to the first surface 10a and having a second metal layer 11b disposed thereon, and a plurality of through holes 100 penetrating the first and second surfaces 10a, 10b. 
Referring to FIG. 1B, a patterning process is performed to use the first and second metal layers 11a, 11b (using a conductive layer 12 on the first and second metal layers 11a, 11b as a current conductive path for electroplating) to form a first circuit layer 13a and a second circuit layer 13b on the first surface 10a and the second surface 10b of the core layer 10, respectively, and form a plurality of conductive through holes 14 in the through holes 100 for electrically connecting the first and second circuit layers 13a, 13b. Therein, the first and second circuit layers 13a, 13b have a plurality of first and second conductive pads 130a, 130b, respectively.
Referring to FIG. 1C, a first insulating protection layer 15a and a second insulating protection layer 15b are formed on the first surface 10a and the second surface 10b of the core layer 10, respectively. The first and second insulating protection layers 15a, 15b have a plurality of first and second openings 150a, 150b for exposing the first and second conductive pads 130a, 130b, respectively. Further, a first surface finish layer 16a and a second surface finish layer 16b are formed on the exposed first and second conductive pads 150a, 150b, respectively.
Subsequently, a semiconductor chip can be disposed on the second insulating protection layer 15b and encapsulated by an encapsulant so as to form a package structure. According to the current processing technology, the thickness S of the packaging substrate 1 can be reduced to 150 um.
However, such a packaging substrate having a thickness of 150 um is difficult to meet the miniaturization requirement of semiconductor packages. On the other hand, if the thickness of the packaging substrate 1 is reduced to be less than 150 um, the packaging substrate 1 is easy to crack during transportation or packaging, thereby adversely affecting the product yield.
Therefore, there is a need to provide a packaging substrate and a fabrication method thereof so as to overcome the above-described drawbacks.